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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5241/ad5242 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 functional block diagram rdac register 1 addr decode 8 pwr-on reset serial input register ad5241 shdn v dd v ss sda scl gnd a 1 w 1 b 1 o 1 o 2 register 2 ad0 ad1 rdac register 1 addr decode 8 pwr-on reset serial input register ad5242 shdn v dd v ss sda scl gnd a 1 w 1 b 1 a 2 w 2 b 2 rdac register 2 o 2 o 1 register 1 ad0 ad1 features 256 positions 10 k , 100 k , 1 m low tempco 30 ppm/ c internal power on midscale preset single-supply 2.7 v to 5.5 v or dual-supply 2.7 v for ac or bipolar operation i 2 c compatible interface with readback capability extra programmable logic outputs self-contained shutdown feature extended temperature range ?0 c to +105 c applications multimedia, video, and audio communications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage-to-current conversion line impedance matching general description th e ad5241/ad5242 provide a single-/dual-channel, 256- position, digitally controlled variable resistor (vr) device. these devices perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. each vr offers a completely programmable value of resistance between the a te rminal and the wiper, or the b terminal and the wiper. for ad 5242, the fixed a-to-b terminal resistance of 10 k ? , 100 k ? , or 1 m ? has a 1% channel-to-channel matching tolerance. the n ominal temperature coefficient of both parts is 30 ppm/ c. wi p er position programming defaults to midscale at system power on. once powered, the vr wiper position is programmed by an i 2 c compatible 2-wire serial data interface. both parts have available two extra programmable logic outputs that enable users to drive digital loads, logic gates, led drivers, and analog switches in their system. the ad5241/ad5242 are available in surface-mount (soic-14/- 16) packages and, for ultracompact solutions, tssop-14/-16 pack ages. all parts are guaranteed to operate over the extended temperature range of ?0 c to +105 c. for 3-wire, spi compatible interface app lications, p lease refer to ad5200, ad 5201, ad5203, ad5204, ad5206, ad5231 * , ad5232 * , ad5235 * , ad7376, ad8400, ad8402, and ad8403 products. i 2 c compatible 256-position digital potentiometers * nonvolatile digital potentiometer i 2 c is a registered trademark of philips corporation.
rev. b e2e ad5241/ad5242especifications 10 k , 100 k , 1 m version parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode (specifications apply to all vrs.) resistor differential nonlinearity 2 r-dnl r wb , v a = no connect e1 0.4 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect e2 0.5 +2 lsb nominal resistor tolerance dr t a = 25 c, rab = 10 k e30 +30 % dr t a = 25 c, rab = 100 k /1 m e30 +50 % resistance temperature coefficient r ab /dt v ab = v dd , wiper = no connect 30 ppm/ c wiper resistance r w i w = v dd /r, v dd = 3 v or 5 v 60 120 dc characteristics, potentiometer divider mode (specifications apply to all vrs.) resolution n 8 bits differential nonlinearity 3 dnl e1 0.4 +1 lsb integral nonlinearity 3 inl e2 0.5 +2 lsb voltage divider temperature coefficient dv w /dt code = 80 h 5 ppm/ c full-scale error v wfse code = ff h e1 e0.5 0 lsb zero-scale error v wzse code = 00 h 0 0.5 1 lsb resistor terminals voltage range 4 v a, b, w v ss v dd v capacitance 5 a, b c a, b f = 1 mhz, measured to gnd, code = 80 h 45 pf capacitance 5 wc w f = 1 mhz, measured to gnd, code = 80 h 60 pf common-mode leakage i cm v a = v b = v w 1na digital inputs input logic high (sda and scl) v ih 0.7 v dd v dd + 0.5 v input logic low (sda and scl) v il e0.5 +0.3 v dd v input logic high (ad0 and ad1) v ih v dd = 5 v 2.4 v dd v input logic low (ad0 and ad1) v il v dd = 5 v 0 0.8 v input logic high v ih v dd = 3 v 2.1 v dd v input logic low v il v dd = 3 v 0 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 5 c il 3pf digital output v ol i ol = 3 ma 0.4 v output logic low (sda) v ol i ol = 6 ma 0.6 v output logic low (o 1 and o 2 )v ol i sink = 1.6 ma 0.4 v output logic high (o 1 and o 2 )v oh i source = 40 a4v three-state leakage current (sda) i oz v in = 0 v or 5 v 1 a output capacitance 5 c oz 38 pf power supplies power single-supply range v dd range v ss = 0 v 2.7 5.5 v power dual-supply range v dd/ss range 2.3 2.7 v positive supply current i dd v ih = 5 v or v il = 0 v 0.1 50 a negative supply current i ss v ss = e2.5 v, v dd = +2.5 v +0.1 e50 a power dissipation 6 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0.5 250 w power supply sensitivity pss e0.01 +0.002 +0.01 %/% dynamic characteristics 5, 7, 8 bandwidth e3 db bw_10 k r ab = 10 k , code = 80 h 650 khz bw_100 k r ab = 100 k , code = 80 h 69 khz bw_1 m r ab = 1 m , code = 80 h 6 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, 0.005 % v b = 2 v dc, f = 1 khz v w settling time t s v a = v dd , v b = 0 v, 1 lsb error band, 2 s r ab = 10 k resistor noise voltage e n_wb r wb = 5 k , f = 1 khz 14 nv hz
rev. b e3e ad5241/ad5242 parameter symbol conditions min typ 1 max unit interface timing characteristics (applies to all parts. 5, 9 ) scl clock frequency f scl 0 400 khz t buf bus free time between t 1 1.3 s stop and start t hd; sta hold time (repeated start) t 2 after this period, the first clock 600 ns pulse is generated. t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su; sta setup time for repeated start condition t 5 600 ns t hd; dat data hold time t 6 900 ns t su; dat data setup time t 7 100 ns t r rise time of both t 8 300 ns sda and scl signals t f fall time of both sda and scl signals t 9 300 ns t su; sto setup time for stop condition t 10 notes 1 typicals represent average readings at 25 c, v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see test circuits. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 10. 4 resistor terminals a, b, w have no limitations on polarity with respect to each other. 5 guaranteed by design and not subject to production test. 6 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 7 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the fa stest settling time and highest band- width. the highest r value results in the minimum overall power consumption. 8 all dynamic characteristics use v dd = 5 v. 9 see timing diagram for location of measured values. specifications subject to change without notice.
rev. b ad5241/ad5242 e4e absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v, +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v , e7 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v a , v b , v w to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd a x eb x , a x ew x , b x ew x at 10 k in tssop-14 . . . 5.0 ma * a x eb x , a x ew x , b x ew x at 100 k in tssop-14 . . 1.5 ma * a x eb x , a x ew x , b x ew x at 1 m in tssop-14 . . . 0.5 ma * digital input voltage to gnd . . . . . . . . . . . . . . . . . . 0 v, 7 v operating temperature range . . . . . . . . . . e40 c to +105 c thermal resistance ja soic (soic-14) . . . . . . . . . . . . . . . . . . . . . . . . . 158 c/w soic (soic-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 73 c/w tssop-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 c/w tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 c/w maximum junction temperature (t j max) . . . . . . . . . . 150 c package power dissipation p d = (t j max e t a )/ ja storage temperature . . . . . . . . . . . . . . . . . . e65 c to +150 c lead temperatures r-14, r-16a, ru-14, ru-16 (vapor phase, 60 sec) . 215 c r-14, r-16a, ru-14, ru-16 (infrared, 15 sec) . . . . . 220 c * max current increases at lower resistance and different packages. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5241/ad5242 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide number of number of end to end temperature package package devices per model channels r ab ( ) range ( c) description option container ad5241br10 1 10 k e40 to +105 soic-14 r-14 56 ad5241br10-reel7 1 10 k e40 to +105 soic-14 r-14 1000 ad5241bru10-reel7 1 10 k e40 to +105 tssop-14 ru-14 1000 ad5241br100 1 100 k e40 to +105 soic-14 r-14 56 ad5241br100-reel7 1 100 k e40 to +105 soic-14 r-14 1000 ad5241bru100-reel7 1 100 k e40 to +105 tssop-14 ru-14 1000 ad5241br1m 1 1 m e40 to +105 soic-14 r-14 56 ad5241bru1m-reel7 1 1 m e40 to +105 tssop-14 ru-14 1000 ad5242br10 2 10 k e40 to +105 soic-16 r-16a 48 ad5242br10-reel7 2 10 k e40 to +105 soic-16 r-16a 1000 ad5242bru10-reel7 2 10 k e40 to +105 tssop-16 ru-16 1000 ad5242br100 2 100 k e40 to +105 soic-16 r-16a 48 ad5242br100-reel7 2 100 k e40 to +105 soic-16 r-16a 1000 ad5242bru100-reel7 2 100 k e40 to +105 tssop-16 ru-16 1000 ad5242br1m 2 1 m e40 to +105 soic-16 r-16a 48 ad5242bru1m-reel7 2 1 m e40 to +105 tssop-16 ru-16 1000 notes 1 the ad5241/ad5242 die size is 69 mil 78 mil, 5,382 sq. mil. contains 386 transistors for each channel. patent number 5495245 applies. 2 tssop packaged units are only available in 1,000-piece quantity tape and reel.
rev. b e5e ad5241/ad5242 ad5242 pin function descriptions pin mnemonic description 1o 1 logic output terminal o 1 2a 1 resistor terminal a 1 3w 1 wiper terminal w 1 4b 1 resistor terminal b 1 5v dd positive power supply, specified for opera- tion from 2.2 v to 5.5 v. 6 shdn a ww ada shdn dd s s sda sd ad adad ad adad dnd ss n w ww a a adnnan w ns nnnn w dd shdn s sda n ss dnd ad ad a ad adnnan w ns a w dd shdn s sda a w ss dnd ad ad ad adnnndsns d a a w ww dd shdn a ww ada shdn dd s s sda sd a d adad a d adad dnd ss n n n
rev. b ad5241/ad5242 e6e t 8 t 1 t 8 t 3 t 2 t 2 t 9 t 5 t 10 s p t 7 t 4 s p sda scl t 6 figure 1. detail timing diagram data of ad5241/ad5242 is accepted from the i 2 c bus in the following serial format: s01 0 11 ad1 ad0 r/ w a a /b rs sd o 1 o 2 xxxad7d6d5d4d 3d2 d1d0 a p slave address byte instruction byte data byte where: s = start condition p = stop condition a = acknowledge x = don?t care ad1, ad0 = package pin programmable address bits. must be matched with the logic states at pins ad1 and ad0. r/ w = read enable at high and output to sda. write enable at low. a dadada s sdss shdn ddddddddd adad w a s sd d d d d dd dd a ad a ad a ad s as sa as a saaddss a nsn a daa s sda wdas adad w d d d d d d d d a ad na as s as sa as a saaddss a daassd dasnwd s sda dsdaw
rev. b code ?decimal 1.0 0.5 0 ?.5 ?.0 rheostat mode differential nonlinearity ?lsb 256 224 192 160 128 96 64 32 0 v dd /v ss = +2.7v/0v v dd = +2.7v v dd = +5.5v v dd = 2.7v v dd /v ss = +5.5v/0v, 2.7v tpc 1. rdnl vs. code code ?decimal 1.0 0.5 0 ?.5 ?.0 rheostat mode integral nonlinearity ?lsb 224 192 160 128 96 64 32 0 256 v dd /v ss = +5.5v/0v, 2.7v v dd = +2.7v v dd = +5.5v v dd = 2.7v v dd /v ss = +2.7v/0v tpc 2. rinl vs. code code ?decimal 0.25 0.13 0 ?.13 ?.25 potentiometer mode differential nonlinearity ?lsb 256 224 192 160 128 96 64 32 0 v dd /v ss = +2.7v/0v, +5.5v/0v, 2.7v v dd = +2.7v v dd = +5.5v v dd = 2.7v tpc 3. dnl vs. code ? t ypical performance characteristics?d5241/ad5242 code ?decimal 0.50 0.25 0 ?.25 ?.50 potentiometer mode integral nonlinearity ?lsb 256 224 160 128 64 32 0 192 96 v dd = +2.7v v dd = +5.5v v dd = 2.7v v dd /v ss = 2.7v v dd /v ss = +2.7v/0v, +5.5v/0v tpc 4. inl vs. code 10000 100 1 nominal resistance ?k 80 60 40 20 0 ?0 ?0 temperature ? c v dd = 2.7v t a = 25 c 10 1000 10k 1m 100k tpc 5. nominal resistance vs. temperature 10000 1000 100 10 1 i dd - supply current ? a 5 4 3 2 1 0 input logic voltage ?v v dd = 2.5v v dd = 3v v dd = 5v tpc 6. supply current vs. input logic voltage
rev. b ad5241/ad5242 e8e 0.1 0.01 0.001 shutdown current e a 80 60 40 20 0 e20 e40 temperature e c r ab = 10k v dd = 5.5v tpc 7. shutdown current vs. temperature v dd /v ss = 2.7v/0v t a = 25 c 100k version code e decimal 128 96 64 32 0 70 60 20 0 e30 potentiometer mode tempco e ppm/ c 50 40 30 10 e10 e20 10k version 10m version 160 192 224 256 tpc 8. v wb / t potentiometer mode tempco code e decimal 120 100 20 e20 e80 rheostat mode tempco e ppm/ c 256 224 192 160 128 96 64 32 0 80 60 40 0 e40 e60 v dd /v ss = 2.7v/0v t a = 25 c 10k version 10m version 100k version tpc 9. r wb / t rheostat mode tempco t a = 25 c common mode e v 100 90 50 30 wiper resistance e 5 4 3 2 1 0 e1 e2 e3 80 70 60 40 20 10 v dd /v ss = +2.7v/0v 6 v dd /v ss = 2.7v/0v v dd /v ss = +5.5v/0v tpc 10. incremental wiper contact vs. v dd /v ss frequency e khz 300 100 50 0 i dd e supply current a 1000 100 10 150 200 250 e b c a d f a e v dd /v ss = 5.5v/0v code = ff b e v dd /v ss = 3.3v/0v code = ff c e v dd /v ss = 2.5v/0v code = ff d e v dd /v ss = 5.5v/0v code = 55 e e v dd /v ss = 3.3v/0v code = 55 f e v dd /v ss = 2.5v/0v code = 55 tpc 11. supply current vs. frequency frequency e hz 6 e36 e42 e48 e54 gain e db 1m 100k 10k 1k 100 e30 e24 e18 e12 e6 0 ff h 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h tpc 12. ad5242 10 k gain vs. frequency vs. code
rev. b e9e ad5241/ad5242 operation the ad5241/ad5242 provide a single-/dual-channel, 256- position digitally controlled variable resistor (vr) device. the terms vr, rdac, and programmable resistor are commonly used interchangeably to refer to digital potentiometer. to program the vr settings, refer to the digital interface sec- tion. both parts have an internal power on preset that places th e wiper in midscale during power-on, which simplifies the fault condition recovery at power-up. in addition, the shutdown shdn adadda a ww d da w da sw shdn sw n sw n da ah and dd a n w da da a sw sw d d d d d d d d shdn da anhaass daa a w da a h s w w a w h h s a s w da s w rd d rr wb ab w () =+ 256 (1) where: d is the decimal equivalent of the binary code between 0 and 255, which is loaded in the 8-bit rdac register. r ab is the nominal end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. again, if r ab = 10 k and the a terminal can be either open circuit or tied to w, the following output resistance at r wb w ill be set for the following rdac latch codes. frequency e hz 6 e36 e42 e48 e54 gain e db 100k 10k 1k 100 e30 e24 e18 e12 e6 0 ff h 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h tpc 13. ad5242 100 k gain vs. frequency vs. code frequency e hz 6 e36 e42 e48 e54 gain e db 100k 10k 1k 100 e30 e24 e18 e12 e6 0 ff h 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h tpc 14. ad5242 1 m gain vs. frequency vs. code
rev. b ad5241/ad5242 e10e dr wb (dec) ( )o utput state 255 10021 full-scale (r wb e 1 lsb + r w ) 128 5060 midscale 199 1 lsb 06 0z ero-scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 60 is present. care should be taken to limit the current flow between w and b in this state to a maximum current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digi- tally controlled resistance, r wa . when these terminals are used, the b terminal can be opened or tied to the wiper terminal. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is: rd d rr wa ab w () =+ 256 256 e (2) for r ab = 10 k , and the b terminal can be either open circuit or tied to w. the following output resistance r wa will be set for the following rdac latch codes. dr wa (dec) ( ) output state 255 99 full-scale 128 5060 midscale 1 10021 1 lsb 0 10060 zero-scale the typical distribution of the nominal resistance r ab from channel to channel matches within 1% for ad5242. device- to-device matching is process lot dependent and it is possible to have 30% variation. since the resistance element is processed in thin film technology, the change in r ab with temperature has no more than a 30 ppm/ c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer easily generates output voltages at wiper-to-b and wiper-to-a to be proportional to the input volt- age at a-to-b. unlike the polarity of v dd e v ss , which must be positive, voltage across aeb, wea, and web can be at either polarity provided that v ss is powered by a negative supply. if ignoring the effect of the wiper resistance for approximation, connecting the a terminal to 5 v and the b terminal to ground pro duces an output voltage at the wiper-to-b starting at 0 v up to 1 ls b less than 5 v. each lsb of voltage is equal to the voltage ap plied across terminal ab divided by the 256 positions of the potentiometer divider. since ad5241/ad5242 can be sup- plied by dual supplies, the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminals a and b is: vd d v d v wa b () =+ ? 256 256 256 (3) which can be simplified to vd d vv wabb () =+ 256 (4) where d is the decimal equivalent of the binary code between 0 to 255 that is loaded in the 8-bit rdac register. for more accurate calculation including the effects of wiper resistance, v w can be found as: vd rd r v rd r v w wb ab a wa ab b () = () + () (5) where r wb ( d ) and r wa ( d ) can be obtained from equations 1 and 2. operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the r heo stat mode, the output voltage is dependent on the ratio of the internal resistors r wa and r wb , and not the absolute values; therefore, the temperature drift reduces to 5 ppm/ c. digital interface 2-wire serial bus the ad5241/ad5242 are controlled via an i 2 c compatible serial bus. the rdacs are connected to this bus as slave devices. referring to figures 2 and 3, the first byte of ad5241/ad5242 is a slave address byte. it has a 7-bit slave address and an r/ w s adad ad ad sa sda s sa w sda aa w w aw w sas a da a dada ads a ad ssa da wa w ssda sddaa sd shdn
rev. b e11e ad5241/ad5242 pin except that shdn d sds a wdd a sdas s wd sa d wn as sda sss wds as sda s wsda s na sda sda s aw da dwd dada sa da da ws ad s da adadaa sad w da daw ds da da w da wd dsnns ad ad adda n ad ad sa adad sdas ad ad ad sda s sdas ad dd ad ad sdas ad ad ad dd sdas ad dd ad ad as add shdnana w w a nn dn dd sd sd ad s sda dd s sda dd sdd n dd v ss m p m n o 1 data in frame 2 of write mode figure 7. output stage of logic output o 1 additional programmable logic output ad5241/ad5242 feature additional programmable logic out- puts, o 1 and o 2, that can be used to drive digital load, analog switches, and logic gates. they can also be used as self-con- tained shutdown as preset to logic 0 feature which will be explained later. o 1 and o 2 default to logic 0 during power-up. the logic states of o 1 and o 2 can be programmed in frame 2 under the write mode (see figure 2). figure 7 shows the out- put stage of o 1 which employs large p and n channel mosfets in push-pull configuration. as shown, the output will be equal to v dd or v ss , and these logic outputs have adequate current driving capability to drive milliamperes of load.
rev. b ad5241/ad5242 e12e users can also activate o 1 and o 2 in three different ways with- out affecting the wiper settings. 1. start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. 2. complete the write cycle with stop, then start, slave ad dress byte, acknowledge, instruction byte with o 1 and o 2 speci- fied, acknowledge, stop. 3. do not complete the write cycle by not issuing the stop, then start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. all digital inputs are protected with a series input resistor and parallel zener esd structures shown in figure 9. this applies to digital input pins sda, scl, and shdn snandshdwnnn s shdn sdw sda shdn s d s ss sdd aw ss sd
rev. b e13e ad5241/ad5242 t est circuits test circuits 1 to 9 define the test conditions used in the product specifications table. v ms a w b dut v v+ = v dd 1lsb = v+/2 n test circuit 1. potentiometer divider nonlinearity error (inl, dnl) no connect i w v ms a w b dut test circuit 2. resistor position nonlinearity error (rheo- stat operation; r-inl, r-dnl) v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 e v ms2 ]/i w a w b dut test circuit 3. wiper resistance v ms % v dd % pss (%/%) = v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) v dd v a v ms a w b v+ test circuit 4. power supply sensitivity (pss, psrr) op279 w 5v b v out offset gnd offset bias a dut test circuit 5. inverting gain b a v in op279 w 5v v out offset gnd offset bias dut test circuit 6. noninverting gain +15v e15v w a 2.5v b v out offset gnd dut op42 v in test circuit 7. gain vs. frequency w b v ss to v dd dut i sw code = h r sw = 0.1v i sw 0.1v test circuit 8. incremental on resistance w b v cm i cm a nc gnd nc v ss v dd dut test circuit 9. common-mode leakage current
rev. b ad5241/ad5242 e14e digital potentiometer selection guide number resolution power of vrs terminal interface nominal (number supply part per voltage data resistance of wiper current number package 1 range control 2 (k ) positions) (i dd )p ackages comments ad5201 1 3 v, +5.5 v 3-wire 10, 50 33 40 a msop-10 full ac specs, dual supply, power-on-reset, low cost ad5220 1 5.5 v up/down 10, 50, 100 128 40 a pdip, so-8, msop-8 no rollover, power-on-reset ad7376 1 15 v, +28 v 3-wire 10, 50, 100, 1000 128 100 a pdip-14, sol-16, single 28 v or dual 15 v tssop-14 supply operation ad5200 1 3 v, +5.5 v 3-wire 10, 50 256 40 a msop-10 full ac specs, dual supply, power-on-reset ad8400 1 5.5 v 3-wire 1, 10, 50, 100 256 5 a soic-8 full ac specs ad5241 1 3 v, +5.5 v 2-wire 10, 100, 1000 256 50 a soic-14, tssop-14 i 2 c compatible, tc < 50 ppm/ c ad5231 1 2.75 v, +5.5 v 3-wire 10, 50, 100 1024 10 a tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5260 1 5 v, +15 v 3-wire 20, 50, 200 256 60 a tssop-14 tc < 50 ppm/ c ad5207 2 3 v, +5.5 v 3-wire 10, 50, 100 256 40 a tssop-14 full ac specs, svo ad5222 2 3 v, +5.5 v up/down 10, 50, 100, 1000 128 80 a soic-14, tssop-14 no roll over, stereo, power-on- reset, tc < 50 ppm/ c ad8402 2 5.5 v 3-wire 1, 10, 50, 100 256 5 a pdip, soic-14, full ac specs, na tssop-14 shutdown current ad5232 2 2.75 v, +5.5 v 3-wire 10, 50, 100 256 10 a tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5235 2 2.75 v, +5.5 v 3-wire 25, 250 1024 5 a tssop-16 nonvolatile memory, tc < 50 ppm/ c ad5242 2 3 v, +5.5 v 2-wire 10, 100, 1000 256 50 a soic-16, tssop-16 i 2 c compatible, tc < 50 ppm/ c ad5262 2 5 v, +12 v 3-wire 20, 50, 200 256 60 a tssop-16 medium voltage operation, tc < 50 ppm/ c ad5203 4 5.5 v 3-wire 10, 100 64 5 a pdip, sol-24, full ac specs, na tssop-24 shutdown current ad5233 4 2.75 v, +5.5 v 3-wire 10, 50, 100 64 10 a tssop-24 nonvolatile memory, direct program, i/d, 6 db settability ad5204 4 3 v, +5.5 v 3-wire 10, 50, 100 256 60 a pdip, sol-24, full ac specs, dual supply, tssop-24 power-on-reset ad8403 4 5.5 v 3-wire 1, 10, 50, 100 256 5 a pdip, sol-24, full ac specs, na tssop-24 shutdown current ad5206 6 3 v, +5.5 v 3-wire 10, 50, 100 256 60 a pdip, sol-24, full ac specs, dual supply, tssop-24 power-on-reset notes 1 vr stands for variable resistor. this term is used interchangeably with rdac, programmable resistor, and digital potentiometer. 2 3-wire interface is spi and microwire compatible. 2-wire interface is i 2 c compatible.
rev. b e15e ad5241/ad5242 outline dimensions 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 coplanarity compliant to jedec standards mo-153ab 16-lead standard small outline package [soic] narrow body (r-16a) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012 ac 16 9 8 1 4.00 (0.1575) 3.80 (0.1496) 10.00 (0.3937) 9.80 (0.3858) 1.27 (0.0500) bsc pin 1 6.20 (0.2441) 5.80 (0.2283) seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 1.75 (0.0689) 1.35 (0.0531) 8 0 0.50 (0.0197) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.19 (0.0075) coplanarity 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity compliant to jedec standards mo-153ab-1 14-lead standard small outline package [soic] narrow body (r-14) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012 ab 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) pin 1 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 1.75 (0.0689) 1.35 (0.0531) 8 0 0.50 (0.0197) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.19 (0.0075) coplanarity
?6 printed in u.s.a. c00926??/02(b) rev. b revision history location page 8/02?ata sheet changed from rev. a to rev. b. additions to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 additions to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to tpc 8 and tpc 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 changes to readback rdac value section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to additional programmable logic output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 added self-contained shutdown section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 added new figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to digital potentiometer selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/02?ata sheet changed from rev. 0 to rev. a. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to functional block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to figures 1, 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 addition of readback rdac value and additional programmable logic output sections, and addition of new figure 7 (which changed succeeding figure numbers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 additions/edits to digital potentiometer selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ad5241/ad5242

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